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hi,
Can anyone please clarify-
1. I have read somewhere that while in the holding mode, the input common mode voltage of the differential amplifier is equals to output common mode. Does that necessitates the vcmin range should include vcmout? If not what will happen?
2. what should be the...
yes, I know that, but what I have asked is that what should be the formulas after considering the channel length modulation effect?
according to razavi he has all three of them but they do not match
hi, while reading design of analog cmos integrated circuits by razavi chapter 2, he has two of gm expressions with
gm=1/2*k*W/L*(vgs-vth)*(1+lambda*vds) and sqrt((2Id*K*W/L)/(1+lambda*vds)). To my understanding, they both should have been same after
expressing vgs-vth in terms of Id but they...
I have done a simple s parameter analysis for a n channel mosfet in 130nm technology with both the schematic and extracted view. The input impedance with extracted view is almost three times larger than with schematic, is it acceptable? To my understanding it should decrease right? as the...
@dick_freebird I have not fully understood what you have said but if it is a matter to bias the mosfet in saturation region I did that, still there is discrepancy in the results.
@leo_o2 in s parameter analysis you can bias the MOSFET and then run the analysis
Hi,
I have built a circuit with a small ac signal imposed on the dc bias voltage in the gate of the MOSFET and also a dc bias voltage at the drain. It does give me some result. But when I do the s parameter analysis on that device with same configuration and same bias conditions, the s...
Hi,
I want to know how to measure input/output impedance of a device. Can I just do the s parameter analysis and then find out z parameters? Will that be enough?
Hi,
I am just a beginner in layout. I am using cmrf6sf technology in cadence. After choosing nfet_rf part from cmrf6sf library, it shows two gate connections. I just wanted to know while connecting gates of nfet_rf and pfet_rf do I need to connect both?
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