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Recent content by name_windy

  1. N

    [SOLVED] N-well(NW) and N-wel for high voltage(NWH) in smic18pf

    Hi erikl, Thank you for your reply, and i am sorry for replying your post so late.
  2. N

    how do routing for MIM capacitor? failed in LVS

    You can look over your LVS rule, it has the definiton for the pos and neg of the capcitance.
  3. N

    [SOLVED] N-well(NW) and N-wel for high voltage(NWH) in smic18pf

    Hi erikl, I know your meanings. The tolerance voltage of the PN junction has relation with the doping concentrations of the P and N. But i meant the doping concentrations of the P and N near by the depletion layer is still the NWH and P-sub. How about the tolerance voltage of this PN junction?
  4. N

    [SOLVED] N-well(NW) and N-wel for high voltage(NWH) in smic18pf

    Re: N-well (NW) and N-well for high voltage (NWH) in smic18pf I'm also using the smic18pf now. As his picture shown, it isn't disobey the design rule of the smic18pf. And i know the difference between the NW and NWH. So i just confused about the NW in the NWH. Although we don't draw the layout...
  5. N

    [SOLVED] N-well(NW) and N-wel for high voltage(NWH) in smic18pf

    hello, Can you tell me why do you draw an NW in the NWH? Although this is not disobey the design rule, but it is queer.
  6. N

    two-stage OP DC voltage at its inputs: presim versus post-sim

    The gain is negative just because the input voltage has 20mV~30mV difference. please tell me the structure and the bias current of the OP1. And you can add a cap to your schematic between the OP1 output and the gate of ML1, which is about 5~10pf. Then you can run a simulation, tell me the result.
  7. N

    two-stage OP DC voltage at its inputs: presim versus post-sim

    I'm confused about the circuit. It shouldn't be so much mismatch with this matching style. So i think you should check the OP1. Is the gain or driving force of the OP1 enough? As your picture shown, the ML1 is used as power mos. isn't it? So i think it's large amount of mosfet.
  8. N

    two-stage OP DC voltage at its inputs: presim versus post-sim

    How did you match the MN3 and M2? How did you match the input differential transistor of the OP1?
  9. N

    current mirror: presim versus post-sim

    I'm sorry. i don't know your structure so i can't give you some useful advice. Maybe your layout have some problem. you can upload the curve of the simulation about the OP both the pre and post. Did you notice any difference of the VB2 between pre-simulation and post-simulation?
  10. N

    current mirror: presim versus post-sim

    I think the problem is the OPB.
  11. N

    Please help me with the H-precision OSC

    Hello everybody, I'm now designing an oscillator with 0.25% precision (the frequency of the OSC is 12M). This tolerance includes inaccurancies from temperature and supply voltage after the calibration. Anybody who has been designed similar circuit? Please give me some help or some papers...
  12. N

    About the offset voltage tempterature drift of the OPA

    Thank you for your reply, elbadry. And i just want to know the magnitude of the offset voltage tempterature drift. how much will it change as the tempterature? several mV or uV?
  13. N

    About the offset voltage tempterature drift of the OPA

    Hello everyone I am designing a bandgap recently, and i want to know something about the offset voltage tempterature drift of the OPA. Can anybody help me? Thanks a lot! windy
  14. N

    Pin and Netlist Problem , IC Station, Calibre PEX

    pin pex br Hello seen25, I also met this kind of questions before. Maybe the bidirectional port can't be recognized. You can have a try to change them with one directional port. May be helpful. Thanks.
  15. N

    Analog and Digital Design

    I think both of them is good. But most important is which one you are interested in.
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