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Recent content by Nabeel Anjum

  1. N

    Fixed Point operation with std_logic_vector in vhdl

    Ok. I will change those std_logic_vectors to unsigned . And shared variables has a reason, as need to use such inside process for some temp values. but other than that, how can i get such require value (-1.4 )
  2. N

    Fixed Point operation with std_logic_vector in vhdl

    I have fixed_point input and std_logic_Vector. let signal h0: std_logic_vector (31 downto 0) ; signal h1: std_logic_vector (31 downto 0) ; signal h2: std_logic_vector (31 downto 0) ; signal FIX,temp: std_logic_vector (31 downto 0) ; signal out: std_logic_vector (31 downto 0) ; shared variable...

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