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Fixed Point operation with std_logic_vector in vhdl

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Nabeel Anjum

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I have fixed_point input and std_logic_Vector. let

Code:
signal h0: std_logic_vector (31 downto 0) ;
signal h1: std_logic_vector (31 downto 0) ;
signal h2: std_logic_vector (31 downto 0) ;
signal FIX,temp: std_logic_vector (31 downto 0) ;
signal out: std_logic_vector (31 downto 0) ;
shared variable f1,f2 :ufixed (7 downto -24);
shared variable s : sfixed (7 downto -24 ); 

 h0<= x"00000002";
 h1<= x"00000003",
 h3 <= x"00000004"; 
 fix <= x"00000033" ; -- 0.2 in floating point. 

temp <= h1 + (Fix * (h0-(  (h1 sll 1) + h2 ) ); 
        f1:= to_ufixed(unsigned (temp));
If i calculate these values by hand : then it would be

out <= 3 + [ 0.2 * (2 -(6 + 4 ) ) ] = 3 + [0.2 * -8 ] = 3 - 1.6 = 1.4 .

but my output in vhdl is not according to 1.4.

Kindly tell me the appropriate way to achieve that result : As the above operation has negative value too (-8, -1.6) . i also tried to convert it into s-fixed but still some error in the answer. i want fixed output in 8 integers and 24 fractional part.

thanks

Reagrds
 

TrickyDicky

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Why are you doing arithmatic with std_logic_vectors - they are not numbers, they are just collections of bits, and have no numerical meaning. You need to convert them to an appropriate type so they have a meaning (like sfixed, or ufixed)

Also - why have you got shared variables?
 

Nabeel Anjum

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Ok. I will change those std_logic_vectors to unsigned . And shared variables has a reason, as need to use such inside process for some temp values.

but other than that, how can i get such require value (-1.4 )
 

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