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PSS just describes an analysis that can be performed using different methods e.g. shooting or HB. ADS has their version of PSS but it only uses HB. I agree that what we all call "PSS" in industry usually means Spectre's but ngspice also does PSS and so does ADS albeit its not as nice.
Maybe I...
Hi, I use Spectre for all my analog design simulations. Unfortunately, I am writing a proposal that requires some simulations and I cannot simulate using Virtuoso/Spectre for legal reasons. I need to simulate an N-Path filter "like" circuit and require PSS, PAC and Pnoise or some alternative...
Hi, Im getting used to using "optimize_registers" in dc for retiming, everything that I'm doing seems to be working. However, I do get this output message during the optimization:
Warning: The output port 'CTL_SP[28]' has output rise and fall delay
that is smaller than the estimated...
Design Compiler Register Retiming and Synchronization
Hi, I'm using the following command to retime a design in DC:
optimize_registers -sync_transform decompose -async_transform decompose
I now need to change my design in such a way that adds synchronizers for 2 inputs. How can I tell DC not...
Attached below is a simplified schematic showing the circuit and feedback. Also shown is a simplified diagram of how and why Im sending the reset through a synchronizer even though the DFF's are synchronous reset. The "load" signal loads "load_val" into the shift register via a selector mux and...
How else can you guarantee that just after power-up the registers are in a known state?
I guess if you use some pull-ups/downs you can do it but thats probably not the best design practice.
I have synthesized a shift-register with feedback and adjustable feedback taps. I have two questions:
1) The SR has a load and a reset, both synchronous. Both load and reset signals come from off-chip and are not synchronous to the clk so I have sent them both through FIFO synchronizers. My...
Its not by much, ~20ps, I guess Im splitting hairs but yes, its better for the smaller designs.
The wireload model is the standard model that comes with the PDK, in this case, TSMC65. What I meant by "more accurate" is that the P+R tool takes into account wire length.
Im not too worried...
OK, let me address #1:
The test setup consists of an FPGA that is sending the data to the ASIC's internal shift register. I can constrain the FPGA to output the data on the rising clock edge. The in2reg setup and hold time slacks are 1ns and 750ps respectively so I really doubt there will be a...
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