Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi kaz1,
No, it’s not a constant. It’s sometimes written, but the write enable is low for some time after reset. I know it’s always safe to sync reset deassertion, but wanted to understand what would happen if it was not done.
Hi dick_freebird,
Thanks for the answer, but let me confirm for...
Hi experts,
I have a register whose async reset is not synchronized for deassertion. When I deassert reset for this register, will metastability occur if the D input is same as the current Q pin? (I.e., write enable is low for this register)
May I omit the synchronizer in this case?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
