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Recent content by muralinelavalli

  1. M

    What is ADSP++ and how is it used for speech processing?

    CAN ANYBODY EXPLAINS WHAT IS ADSP++,AND HOW IT IS USEFUL FOR SPEECH PROCESSING
  2. M

    VLSI INDUSTRY -FIRING EMPLOYEES

    IS VLSI INDUSTRY IN INDIA GOING THROUGH TOUGH TIME? I WAS FRESHER IN VLSI FIELD ,I NEVER FOUND OPENINGS ANY WHERE I HEARD COMPANIES ARE FIRING LIKE ANYTHING? CAN ANYBODY BIG TECHIE IN VLSI FIELD CAN PREDICT ITS FUTURE
  3. M

    Synchronous vs Asynchronous design

    what is password for rar file?
  4. M

    Can any one tell which are the good books for functional ver

    Can any one tell which are the good books for functional verification?
  5. M

    Noise margin physical interpretation in VLSI circuits

    can any body explain about noise margin physical interpretation in vlsi circuits
  6. M

    LDPC DECODER ARCHITECTURE

    ldpc tutorial i'm trying to model ldpc decoder in verilog , but i need any worked out example how really decoding is done at reciever side using sum-product algorithm,[b] can anybody send tutorials on LDPC DECODER ARCHITECTURES
  7. M

    Need help. ASIC or FPGA?

    it does'nt matter , but the difference in two verification approaches will depends on flow charts (ASIC& FPGA) so u can better exposed to both
  8. M

    started working in field of ASICS and FPGA....

    Depends upon your application a FPGA or ASIC Added after 30 seconds: Depends upon your application a FPGA or ASIC
  9. M

    LDPC decoder architecture

    hi i need an efficient LDPC decoder architecture to model in an verilog can any explain about bp algorithm in ldpc decoding and how to generate H matrix thanks in advance
  10. M

    any sasken placement papers

    i had an saken , can any body sent me model of paper ,i'm doing m.tech in vlsi
  11. M

    Exercise problems in FSM

    engineering digital design by richard.f.tinder is good book
  12. M

    Block level architecture of Divide by 11 circuit

    Divide by 11 circuit mod-11 counter with 4 dfliflops,and eliminating the unused states . u can get it from tocci
  13. M

    When do hold time violations occur?

    Hold time The hold time is the amount of time that data input signals are to be held past the clock rising edge or falling edge. From the defination,
  14. M

    Suggest the best book for digital logic design using state machines

    digital design tinder is best for state machine designing
  15. M

    how to simualte CMRR for diffrential amp?

    CMRR is depended from transistors matching, especially transistor matching of differential pair. That is why simple ac analisys cann't predict resonable results. It's necessary to perform monte-carlo analysis for get results close to reality. Or introduce missmatch manually in schematic (only...
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