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sorry ,FPGA does not support floating operation. in FPGA world ,you can just do all your work with '1' or '0'.
in fact you caculate floating numbers in dsp or mcu ,because in the dsp or mcu ,we use some Algorithm instead of direct floating operation,with make you act as operating floating...
assign sum5=D2 + {D2[23],D2[23:1]}; //mean :i think you don't understand the connection symbol{ }. because the verilog support bit operation,so{D2[23],D2[23:1]}; means a new data contruct by D2[23],D2[23:1].the new data's highest bit is D2[23],and the rest is D2[23:1].
an easy example...
i think you can easily have a quick learn to verilog.it not much different .
i learned vhdl first ,but now i use verilog more . they are very similar .
Failed to find 'glbl' in hierarchical name. - Xilinx User Community Forums
I meet the same problem ,I check the xilinx ,then the above can solve it.
notice this
vsim work.my_design work.glbl
be care the work.glbl
HELLO,PLEASE GIVE SOME ADVISE,
I AM DESIGNING MY FPGA BORAD ,AND I WANT TO MAKE COMMUNICATION WITH PC THROUGH USB.I WANT TO KNOW HOW I CAN DO THAT,INCLUDING HARDWARE AND SOFTWARE,OR INTREDUCE ANY BOOKS FOR ME .
THANKS A LOT.
NICE DAY.
How to generate delay?
DESIGN A COUNTER AND BE CAREFUL WITH YOU SYSTEM CLOCK FOR EXAMPLE YOU HAVE A CLOCK FO 40M ,25ns FOR ONE CYCLE.YOU WILL DESIGN A COUNTER OF (30S+2S)/25NS
IT ISN'T VERY DIFFICULT,IS IT?
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