Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
mc145170-2
If it's not the surrounding of Loop filter and layout, Did you simulate the PLL? (For phase a Gain margin) It might be on the edge of stability. You can use Pspice for simulation.
I used this configuration with npn transistors for AMP from DC - to 120Mhz 0-70v output.
So, you can take Ce and Cin out but you will have to take care for the DC Bias level - in temeperature etc.
The gain will be
G=Vout÷Vin ≈ Rd÷Re (from ≈ dc to fc)
Use this sw to get more info about performences of diffrent capacitors.
In general-
1. Electrolytic capacitors - use for low cost, High ripple curent, low ESR and shorter MTBF and high cap value. 1UF and above. use For power s.
2. Polyester capacitors- use for High Stability and Reliability...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.