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Recent content by morfozar

  1. M

    bit pattern generator in Cadence Virtuoso

    Hi, how to generate pattern data like: 0000 1000 0100 1100 0010 .... 1111 by changing one variable "State", where State = 0 at 0000 State = 1 at 1000 State = 2 at 0100 ... State = 15 at 1111 The task is to cheks S-parameters of 4 -bit digital attenuator.
  2. M

    [Moved]: PA design matching network optimization

    Hello! Designing power amplifier designers use load pull analysis (particular in ADS), then analyze data and find optimum load impedances in frequency range and build matching network. Optimization this network with transistors model is quite slow. Is it possible to extract simple SNP file with...
  3. M

    package simulation in ADS

    Hello! Did anyone use QFN Package design kit, that is included in ADS? Also there are package design kits from Amkor and STATSChipPAC with only QFN packages. Is result good in comparasion with real measurement? And is that technique fit to other packages, SOT for example? I'm asking because it...
  4. M

    wide band amplifiers + paper

    Hi, by changing control voltage Vcn that applied to the gates of M4,M5 you can change its current Ids and respectively its gm
  5. M

    Cadence Virtuoso mixer simulation setup

    Hi, try something like that or just google "cadence mixer simulation tutorial" and you could fing a lot of tutorials
  6. M

    S Parameter in spectre and ADS

    Hello. Define in S parameters box in ADS your input and output ports (inset Noise). Then plot NF (port that you define as output).
  7. M

    buffer in cadence virtuoso

    Hello. It's working without voltage supply, just connect input to NC+, output to PLUS pin and ground other pins.
  8. M

    quadrature vco simulation in ads

    pancho_hideboo, Spectre log file Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 13.1.1.252.isr11 64bit -- 14 Aug 2014 Copyright (C) 1989-2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design...
  9. M

    quadrature vco simulation in ads

    pancho_hideboo, I used PSS with HB in Cadence Spectre. In ADS I tried to use HB without OscPort, but result was the same 36.77GHz with 65mV output voltage. I simulated circuit with OscTest and got following results. The circuit need to resonate when phase cross 0 point and magnitude more then...
  10. M

    quadrature vco simulation in ads

    Hello. I design quadrature VCO in ADS. What is the best place for Oscport in below circuit? I read recommendations for Oscport in negative resistance oscillators (page 8). I can use only one port and I put it between resonator and negative resistance pair. When I simulated output frequency...
  11. M

    number of analog chips per minimum feature size

    I mean minimum size of a transistor on a chip, for example, 1 um, 0.5 um, 0.35um, 0.25 um, 90 nm, etc
  12. M

    number of analog chips per minimum feature size

    Hello! Did anybody see or know where I can find figure "number of produced analog chips per minimum feature size"? Thanks advance
  13. M

    2 to 4 decoder circuit patent

    If somebody needs it I found this structure in patent US6243319 B1 Fig. 13
  14. M

    2 to 4 decoder circuit patent

    Why not? Such simple circuits doesn't have patents? May be there are patent of more complex system that include such decoder?
  15. M

    2 to 4 decoder circuit patent

    Hello! I want to find patent of 2 to 4 decoder that shown on the attached picture below. I made some key words for it, but didn't receive success with it on Google patent. What is possible key word for this circuit? My key words: 2 bit Decoder 2-to-4 Decoder/Demultiplexer two four decoder...
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