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Recent content by moharaza

  1. M

    HSPICE power calculation help: AVG power vs Integrated Power

    no, it does not have inductors. I tried with sample circuit, on that test circuit the figures were close. But, for a full adder it is very different.
  2. M

    HSPICE power calculation help: AVG power vs Integrated Power

    Hi, I am having a problem with power calculation in HSPICE. 1. I calculated power with AVG power command. 2. I integrated current over the period and multiplied with vdd, then divided the energy with period to get the power. surprisingly those power numbers are different. over a 500 cycles, I...
  3. M

    HSPICE cache power calculation

    Hi, I am trying to design a cache with new type of devices. for 1 bit/2bit memory I am generating netlist and doing simulation on hspice. But, I want to know how to do it for 32KB to say 16MB, how do I calculate the power exactly for those bigger circuits. surely generating netlist and...
  4. M

    can source voltage be greater then drain voltage?

    Hi guys, I am stuck with a problem in my research. problem is-- as the signal passes through multiple stages the signal strength decreases. I want a 32bit AND on single dynamic gate(for example), the signal strength starts to decrease as it passes each transistor. what is the remedy for...
  5. M

    VGA display with XUPV2P board - hello world program needed

    VGA with XUPV2P Hi Gurus, I am stuck with my course project. I am trying to display FIR output to monitor using XUPV2P board. But, the problem is- I dont have "hello world" type reference to display anything on monitor using the board. there are few resources on the internet for Spartan3...
  6. M

    Setting a dynamic ROM accessible to all modules in VHDL or Verilog

    Re: Dynamic ROM I am sorry, I dont understand... you want something that involves calculator, cpu, uP ?? please specify precisely what you want.
  7. M

    Setting a dynamic ROM accessible to all modules in VHDL or Verilog

    Re: Dynamic ROM Hi, I am trying to use "unfriendly" VHDL for my project, this is the first time I am doing something with VHDL and I have ran into something horrific. the synthesis tool says-- FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application has discovered an...
  8. M

    Setting a dynamic ROM accessible to all modules in VHDL or Verilog

    Dynamic ROM wow, you are quick. Thanks.
  9. M

    Setting a dynamic ROM accessible to all modules in VHDL or Verilog

    Re: Dynamic ROM I am still confused. Package will contain the declaration, top entity will define it and entities in the lower hierarchy will collect information via their IN port. But, I want the lower level entities to behave as if they are dealing with a ROM. A cache memory concept is...
  10. M

    Setting a dynamic ROM accessible to all modules in VHDL or Verilog

    what is dynamic rom Hi, Sorry for being late. Thanks for your reply. well, the wiring through the hierarchy is a solution. But, I am having difficulties to visualize how it will affect the whole design. Say, if the array contains 1024 words, would it be feasible to pass the array through the...
  11. M

    Setting a dynamic ROM accessible to all modules in VHDL or Verilog

    Hi guys, I badly need some help. Thing is-- I want to load some words into memory dynamically that should be available to all modules. here is the explanation-- I want to put output of an algorithm(32 words) into a memory that holds 32 word. and I want this chunk of memory to be available to...
  12. M

    Help me with designing a modular exponential unit for a thesis

    thesis in crisis Thank you very much FvM, Now, everything is working fine with the inclusion of following codes-- always @ (posedge clk) begin done_v <= done; if (done && ~done_v) outlatch <= out; end CASE DISMISS!! Thank you Thank you Edaboard
  13. M

    Help me with designing a modular exponential unit for a thesis

    Re: thesis in crisis hi, the design in crisis.rar and the one without intending on the post is almost same. (in rar i tried with non blocking statements), but in hardware test, results were same for both sadly. by out!=0 on my previous post, i wanted to defend that the design is working...
  14. M

    Help me with designing a modular exponential unit for a thesis

    Re: thesis in crisis hi, out !=0 always, please check the following testbench, after done=1, and out=result, the value of done and out will switch back to 'zero', when there is new operand on M,e or base. `timescale 1ns/1ps module testa_tb_0; reg clk = 1'b0; reg reset = 1'b0...
  15. M

    Help me with designing a modular exponential unit for a thesis

    Re: thesis in crisis I used very trivial technique to varify, LEDs and Switches, i used only 4 bits and manual inputs through pinouts and switches, from post synthesis simulation report i get the following info-- INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM...
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