Setting a dynamic ROM accessible to all modules in VHDL or Verilog

[moharaza]

Hi guys,

I badly need some help. Thing is-- I want to load some words into memory dynamically that should be available to all modules.

here is the explanation--

I want to put output of an algorithm(32 words) into a memory that holds 32 word. and I want this chunk of memory to be available to other design units too.

But, the problem is- contents of the memory depends on input operands and logics. other blocks use this memory once it is loaded. how do I create a modular design that will solve this problem?

I am using verilog.



Thanks in advance.

 

[FvM]

rom design dynamic

To be accessible allover the design, the data entity has to be wired through the hierarchy, as any other global resource. Unless the access from different places can be completely serialized, the data has to be presented in parallel, as an array of register bits. Verilog is rather restricted in this regard, it doesn't allow multidimensional or structured data types. So the array of words has to be mapped to a one-dimensional array. But this is just a question of readability and doesn't change the basic logic operation.

In VHDL designs, you can have design wide defined data types and also alias signals to access individual data elements.

 

[moharaza]

what is dynamic rom

Hi,

Sorry for being late.

Thanks for your reply. well, the wiring through the hierarchy is a solution. But, I am having difficulties to visualize how it will affect the whole design. Say, if the array contains 1024 words, would it be feasible to pass the array through the hierarchy as a port?

Can you insinuate a bit more about VHDL -"design wide defined data types"concept.. any tutorial or design example?

 

[FvM]

dynamic rom

But, I am having difficulties to visualize how it will affect the whole design.

That's rather simple, I think. The HDL compiler only considers connections that are actually used in the design. There may be special issues, when separately compiling design partitions.

Regarding the VHDL way, you should have a package with global definitions that's imported by all design entities, it can contain e.g.

CONSTANT MAXREG: integer := 255;
TYPE REGS_TYPE is array (0 to MAXREG) of STD_LOGIC_VECTOR(15 downto 0);

The global signal has to be defined once in the top entity and connected to all component instances, that are using it. Depending on the intended purpose, the respective ports can be defined as IN or INOUT.

SIGNAL regs: REGS_TYPE;

 

[moharaza]

Re: Dynamic ROM

I am still confused.

Package will contain the declaration, top entity will define it and entities in the lower hierarchy will collect information via their IN port.

But, I want the lower level entities to behave as if they are dealing with a ROM.

A cache memory concept is identical to my design. where the top entity populates the cache and lower entities fetch words from the cache. mine is a lookup table.

Now, should the lower level entities behave as if their dealing with IN port which is 2 dimensional register/memory. If the memory size is 1024 word, should lower entities (say 3 of them) take 1024 words via their Input port?

 

[FvM]

Re: Dynamic ROM

But, I want the lower level entities to behave as if they are dealing with a ROM.

What do you mean with but?. The signal can be simply used like a ROM.

But you have to connect any bit, that you want to be optionally accessed. If your structure is 1024*16, this are actually 16384 bits. If the real population of this data structure goes beyond your affordable resource budget, you may try with dual port RAM. But in this case, you have to assign an individual RAM instance for each entity interfacing the ROM data and must wire separate address and data signals through the hierarchy. Within each entity, the access has to be serialized, you can't read two ROM words at the same time.

I'm pretty sure, that you can figure out the detail problems with RAM/ROM usage yourself.

 

[moharaza]

Dynamic ROM

wow, you are quick.

Thanks.

 

[moharaza]

Re: Dynamic ROM

Hi,

I am trying to use "unfriendly" VHDL for my project, this is the first time I am doing something with VHDL and I have ran into something horrific. the synthesis tool says--

FATAL_ERROR:Xstortability/export/Port_Main.h:143:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at https://www.xilinx.com/support.

the attachment contains a design unit for hamming weight calculation.
the design calculates number of ones and zeros and stores respective position in 2 separate memories. Its a mess with unsigneds and std_logics..


need some help badly

 

[moharaza]

Re: Dynamic ROM

I am sorry, I dont understand... you want something that involves calculator, cpu, uP ??

please specify precisely what you want.