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Hi,
Suppose you have given two netlists and sdf for only one.
Say net1.v net2.v sdf1.v lib.v
-Both the netlist have same libray cells.
-I need to annotate sdf on net1.v netlist
-To annotate sdf I need timing models for net1.v
-but for net2.v, I need normal cells (without timings -specify block)...
Hi,
You can search the file using "find" command. Go to the top most directory and give command
find ./ -name "SYMTYPE.C"
your problem of getting error sometime might be because of some environment variables. Try running in fresh terminal.
Regards
Peer Mohammed
Hi,
I was talking about specifications i.e. you can find negative setup or hold time in specifications itself. And you might be talking about slack, that must always be positive for a circuit to give proper response. anyways thanks for ur reply.
1. In STA you need not to generate test vectors. But in case of Dyn. Timing you need it.
2. In STA you can check the timing analysis. But in DTA you check functionality also.
3. STA is faster than DTA.
4. STA works only for single clock. But its not there in DTA.
Re: Always Block
You can use both blocking and nonblocking assignments in always block.But for better results follow some guide line..
1. For sequential block use nonblocking.
2. For Combinational logic use blocking assignment.
3.Do not mix blocking and nonblocking in single always block.
I think loop delay is the time taken by the signal from output terminal to the input terminal as there is feedback in Latch/FF. I am not sure about this please refer to some other text books.
xor gate with two mux
Hi..
Yes It is Possible to make Xor gate using single 2:1 Mux.
Here is the way
Lets say inputs of xor gate are A and B and output=y
connect select line to A
Connect 0 -> B
and 1 -> B_bar
Re: input impedance
HI
if u check the input impedance using multimeter at the input terminals it will show u the value in some mega ohms. It means it does not draw any current for it operation.
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