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Recent content by missbirdie

  1. M

    VHDL Code of UART on sparan 3e kit

    uart baud vhdl how can i change it to 115200 bps ?? Added after 5 hours 5 minutes: but won't it non accurate division.. i mean isn't the baud rate value should be sharp !! with no fractions !!
  2. M

    Changing Baud rate from 9600 to 115200

    Hello.. how can i change the baud rate from 9600 to 115200 for UART transmitter in the following VHDL code ?? where the baud rate is represented by: constant bit_time: STD_LOGIC_VECTOR (11 downto 0) := X"A28"; & I can't really get the relation between the 9600 & A28 which is 2600 entity...
  3. M

    10% Duty Cycle in VHDL

    writing vhdl code to get 50% duty cycle clock 100 KHz
  4. M

    VHDL Code of UART on sparan 3e kit

    vhdl code and transmission data yeah u were right i even removed them & it worked :D but i have one more question it's said that the baudrate is 9600 from the instruction : constant bit_time: STD_LOGIC_VECTOR (11 downto 0) := X"A28"; & that X"A28" represents 9600 but actually i can't get it...
  5. M

    10% Duty Cycle in VHDL

    duty cycle vhdl How can I implement in VHDL a 10% Duty cycle clock from the 50 MHz clock in spartan 3 ??
  6. M

    What should be the value of load signal in this parallel to serial converter code?

    Hello I need help in the following parallel to serial converter.. what's the value of load should be ?? shall it be like a clock ?? cause in all cases i tried the output is only the last bit in the shift register .. or is there something wrong with the code ??? library IEEE; use...
  7. M

    VHDL Code of UART on sparan 3e kit

    vhdl uart baud generator but how an i connect tdre to ready ?? isn't ready supposed to be 0 initially for the code ?? how can i do this & it's an internal signal ??
  8. M

    VHDL Code of UART on sparan 3e kit

    vhdl code for uart thanks 'll try this.. but won't i need Picoblaze ??? Added after 2 hours 48 minutes: isn't it in this case like a shift register ???
  9. M

    VHDL Code of UART on sparan 3e kit

    vhdl uart code I just wanna send a stream of bits.. & how can i connect the tdre & ready internally ???
  10. M

    VHDL Code of UART on sparan 3e kit

    vhdl code for usart Actually i understood the code finally :D & i think that the tdre should be connected to the Data terminal ready of the pc & the ready with Data set ready signal from the pc..my question is how can i connect these input to specific pins in the RS232 port ?? In the FPGA user...
  11. M

    VHDL Code of UART on sparan 3e kit

    vhdl code for uart Hello I need help in the following VHDL code .. i'm not so good in VHDL so I need someone to explain to me how does this code achieve the UART transmitter plz VHDL Code: ======== entity uart_tx is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC...
  12. M

    Parallel to Serial 36 bits Shift Register

    Because load must be 1 for parallel loading & must be 0 for serial output & the input clock period is 5 ns so i thought to design another clock for the load with period 5*36 = 180 ns with duty cycle 1% just as a trigger to enable parallel load..but the serial output is always zero !!! what do...
  13. M

    VHDL implementation of Digital IF in WiMAX

    why should it be 1/4 of Fs ??
  14. M

    Parallel to Serial 36 bits Shift Register

    If i want to make a shift register to convert 36 bits from parallel to serial & I have a clock of 182 MHz what's the value of the load ??? shall it be a clock of duty cycle not 50% ??
  15. M

    VHDL implementation of Digital IF in WiMAX

    Sorry I meant this link: https://www.altera.com/literature/an/an421.pdf
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