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Recent content by miskod

  1. M

    What kind of logic after synthesis of this rtl

    Suppose, something like that...It will follow to asynchronous sequential logic.
  2. M

    unconstrained array in verilog

    Hi, I don't know if verilog supports that. I think not (don't know if system verilog is better in this way)...but... What would I do in this case is to create simulation script which is doing following: 1: to go through input file and calculate nr. of inputs 2: to create verilog include file...
  3. M

    [SOLVED] Connecting power net by UPF

    Hi All, No answer, but solution found anyway... Following command should be used before any setup of UPF: set upf_create_implicit_supply_sets false Also you need to specify operating conditions. These can be found by report_design command. -----------------------------------------------...
  4. M

    [SOLVED] Connecting power net by UPF

    Hello All, I got really frustrated. I just need to synthesize very small design. But unfortunately I have just library with powered gates. I don't need sophisticated power management. I just need to have properly connected power nets. By normal synthesis I got design with floating power nets. I...
  5. M

    [SOLVED] verilog: how to find max value in the bus

    Please help me...I'm fighting with following problem in the simulation testbench: I have bus of 32*10bit values: ix_puldata[319:0]. I need to find maximum value in this bus. I use following code enclosed in the task: integer j; …. for(j=0;j<32;j=j+1)...
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