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Recent content by Mirzaaur

  1. M

    Xilinx VP2p : Read Back and Active Partial Reconfiguration

    Dear all, Active partial reconfiguration and read back of configuration for Virtex II pro doesnt work if the design has used any of the shift register LUT from xilinx:- I am trying to find a way where I can set a constraint in UCF file so the mapper never use these components by :- CONFIG...
  2. M

    ACTEL FlashPro Lite in Windows 7.

    Dear all, anybody using "FlashPro Lite" for ACTEL in wondows 7? windows 7 doesnt detect the programmer..... I installed the flash pro for windows 7, rebooted the device but still "FlashPro Lite" is not detected on parallel port? any hint any tip? best regards, mirzaaur
  3. M

    Modelsim simulations and VHDL process senstivity List...Request for Advice.

    sorry for late reply, i was away an traveling. you are right that "if you re-assign the clock internally and have 2 processes running off the two different clocks, the simulation would not match the synthesised version" the problem was in when clk1 captures that data it uses a different...
  4. M

    Modelsim simulations and VHDL process senstivity List...Request for Advice.

    Dear TrickyDicky, thanks a lot for your prompt reply and response. finally i figured out what the mess was going in the simulations:- the test bench was reading a text file to inject a serial bit stream, this bit stream was supposed to feed into a fifo 32 bit to cross into a different clock...
  5. M

    Modelsim simulations and VHDL process senstivity List...Request for Advice.

    Dear TrickyDicky and Shnain, first of thanks a lot for you time to reply my question. >>"If it is sensitive to clock, and you have followed the synchronous template properly, you dont need to have other signals in the sensitivity list, only the clock (and reset if you want an async reset)."...
  6. M

    Modelsim simulations and VHDL process senstivity List...Request for Advice.

    Dear all, I need you advice about a strange behavior of the Modelsim 6.5 SE for a VHDL based design. question: if the sensitivity list of a process is not listed with all internally used signal why Modelsim doesn't let the process to trigger assuming that clock is in sensitivity list then it...
  7. M

    what is the effect to chip if latency is high!

    As others friends mentioned longer latency can be result of the pipelined stages. I just want to add my comment that "RESET" mechanism must be designed very carefully specially the "ASSERT" and "RELEASE" of reset with respect to active clock edge. effects fo flawed "reset mechanism":- some...
  8. M

    out put of Tri- State component (TBUF) to a Register in FPGA.

    Dear All, I need advice about using tri-state (TBUF) compnent in FPGA design. question:- if output of tri-state is connected to input of a register then what will be the logic value stored in register while tri-state is in high impedance state? best regards, mirza
  9. M

    Interface between IPs on Chip

    Dear all; I am looking for any good reference paper or any book whihc can describe most of interface standards like , SPI, I2C, to interface between different IPs. any hint or clue is highly appreciated. regards, mirza
  10. M

    VHDL CODING STYPE FOR STATE MACHINES.

    Dear all, I have a doubt about declaring the type for state variables. normall its declared as : type sm is (sate1, stae2, stae3...); signal pr_st, nxt_st: sm; what difference it will make in synthesis or function of circuit if its done like this way constant sate1...
  11. M

    Xilinx synthesis & CLOCK signals

    hi all; in my design I generate local clock using DCM and provide a clock on output of the virtexII. when i try to create timing constraints after synthesis using constraints editor, I don't get the clock signals there. but some other signal which are not clock they are listed as clock. I...
  12. M

    Post Placement & Route Simulation in (Cadence)NC Launch

    hi all, need you advise, or any hint! I am doing post placement and route simulation of a design. in the signal list the hierarchy is not preserved. if i want to probe certain signals of interest I cant find. they have new name...:cry: how to get the original names & signal into wave window...
  13. M

    please guide me about debug mode?

    Dear all, I got a design specification to design my module. there are two different kind of area count (Xilinx FPGA based) Debugg mode Number of Slices: 1) 1824 Number of Slice Flip Flop: 2)1422 Release mod Number of Slices: 1) 1169 Number of Slice Flip Flop: 2)786 my confusion is , what is...
  14. M

    SCHEMATICS AND VHDL....!!GUIDANCE NEEDED...

    dear all, I tried to convert this schamtics into VHDL code. with schmatics simulation it works fine. but VHDL code it gives wrong result in simulation. can any one check if schematics and vhdl code are equilent ??? thanks in advance, mirza library IEEE; use IEEE.STD_LOGIC_1164.ALL; use...
  15. M

    Mixed Simulation of Design (VHDL and Verilog)

    instance verilog in vhdl Dear all, I need to simulate my design with another design which was done already in verilog. module in Verilog will communicate with the Design in VHDL. I did simulation of my Design in VHDL using a test bench, but for practical reasons I need to used the other...
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