Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Miralipoor

  1. M

    [SOLVED] Need help with moving (slow clocked) data using FIFO and DMA to PS of Zynq

    Hi, Unfortunately i could not find your chip (ad79761) . Anyway for troubleshooting try to figure out minimized system. for example you can use simple I/O rather that using DMA. Also check your differential I/O pins and pin numbers.Many thing may occurs you must narrow down your question.What...
  2. M

    [PIC] need help to explain a code

    Hi, With high probability ADRESH and ADRESL are memory mapped register.You can check it by finding definition in header files.For more help you must specify your platform and some more information Regards
  3. M

    Problems with Fourier Transform

    Hi, multiplication in time domain is equivalent of convolution in frequency domain.so you need calculate each part in frequency domain and then convolve them.any way I think your result of primary question is wrong. Regards
  4. M

    How to display frequency spectrum of time-domain signals with simlink/matlab

    Use RMS block
  5. M

    do we need a fifo when read clk freq is greater than write clk freq?

    Hi, It is recommended to synchronize two clock region even those clock have same phase.you can use asynchronous fifo for that purpose. Regards
  6. M

    doubts in digital design concepts

    Hi shainky I am sorry, I am agree with ads-ee. Regards
  7. M

    doubts in digital design concepts

    Hi, Your questions are deep and refers to several aspect of hdl and logic design, also answering whole question briefly is equivalent of writing a digital design book, so I think every one choose one question to be answered or discussed. I choose question 5. 5. Short answer is yes.you can gate...
  8. M

    spartan 3e starter UDP IP ethernet VHDL

    Hi, when you can not see any data, following circumstances may occur 1- you are not able to feed true preamp 2- delimiter byte is missing or is not in true position. 3- frame CRC corrupted or did not calculated correctly. 4- auto negotiation of phy is disabled. I propose to test loopback first...
  9. M

    square root of a number

    Re: square root of a number.............. Hi, Are you have plan to use IEEE-754 floating point format? Your input format is not clear. Reagrds
  10. M

    Matrix Transpose in VHDL

    Hi, you can define matrix n*n of bits in this way type MyMatrix is Array(n-1 downto 0) of std_logic_vector(n-1 downto 0); let define M and MT of MyMatrix the transpose code look like this outer_loop:for i in 0 to n-1 generate inner_loop:for j in 0 to n-1 generate MT(i)(j)<=M(j)(i); end generate...
  11. M

    [SOLVED] Help me to code Parallel MAC unit in verilog.

    you can write your code in any HDL language it does not matter in which language you implement it. Yes ads-ee is right.To get appropriate clock frequency you must form a pipeline based on your design.
  12. M

    project of data transmission wirelessly.

    There is plenty of RF devices that match your requirement.I didn't get why you send such a question.
  13. M

    [SOLVED] Help me to code Parallel MAC unit in verilog.

    you can combine your base module by using vhdl.
  14. M

    Can FPGA filter 0-10MHZ with 10khz resulation??????

    Hi, it doesn't matter how you feed your FFT module.I suggest following link to start your project, you can do your project with some minor modification on it.Just replicate bandpass FIR filter for your desire bands. https://opencores.org/project,fft_fir_filter just simulate it, if you didn't...
  15. M

    what is the fifo depth ?

    anyway your fifo come to be full soon or late regardless of fifo depth because input rate(60Ms/S) is greater than output rate(45Ms/S).
See more

Part and Inventory Search

Back
Top