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DFT :design for test
after manufactured, circuits in a die should be tested to find bad ones, and send good ones to assemble. the test partern are obtained in design stage.
timing differences between pt and dc reports
DC is for synthesis, and can do some simple timing analysis.
but only PT can be a final sign-off STA tool.
PS. they have different algorithm for STA inside themselve.
verilog hdl
verilog can be used for RTL description in front end design, besides, verilog can be for behavial description, extent to a good verifacation language via PLI, and many netlist can be in a verilog format.
Re: DC question
i think not all cells in target library can be use for synthesis, especially for synchronous synthesis, for example, latch should be set_not_use.
a designer should have a clear understanding on cells' usage in lib to obtain a excellent implementation.
application of nanotechnology in vlsi
i think nanotech will pose a challenge on ic design flow, especially in physical implementation, becoz more factors should be considered.
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