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Synopsys LVS error "The following layout port nets equate to non-port schematic nets"
"The following layout port nets equate to non-port schematic nets"
would anyone help me what it mean by this error..
i attach my LVS simulation error picture
hello everyone,
please help me make the output of my rectifier into positive volts..
here is my circuit and waveform output,
the input 0.25V at 2.45GHz the output is approximately neagtive 1.2V
ur help would mean a lot to me :)
hello everyone,
i'm having trouble with this the output of my 3 stage cmos rectifier is 0.4 with input vrf = 0.25V, then if i connect the rectifier to a non-overlapping and self-oscillating clock and a voltage doubler circuit the output of my rectifier becomes 0.16V and the final output of my...
Is there any cmos circuit that subtract 2 voltages which is out-of-phase to each other..
the thing is the input voltages is very low, as low as -/+200mV..
i'm looking for clock dependent differential circuit (it doesn't have a external power supply)
Is there any existing circuit like that...
My project needs a charge pump that can boost a fixed DC voltage (250mV or less) up to a usable DC output (around 1.8V to power an IC). Since it is energy harvesting our teacher said not to use a supply (VDD) and just purely depend on the input as source (that is the 250mV or less). I have tried...
Is there any method or existing circuit that converts a fixed DC voltage to a square wave?..I need the square wave to a clock for switching my main circuit and the only input i can use is a fixed DC voltage. Thanks for any reply.
i cascaded it in such a way that the output of the first stage is the input of the 2nd stage and soon..the clock is equal to all stages..btw, the values of the component in the 2nd stage is the same in the 1st stage..tnx for the reply
Anyone knows why the output of the voltage doubler doesn't increase even though i cascade it up to 3rd stage?..Tnx for any answer. i attach the circuit of the 1st stage voltage doubler with its simulated output.
well i'm just asking if that circuit is really possible...or this one a differential circuit that has low voltage power supply(as low as possible) does it have a possible circuit design?
i'm currently designing RF to DC converter that doesnt require external power supply..
i already have an rectifier design together with its out..
the thing is i need a differential circuit that combines and amplify the negative and positive rectified signals into a single rectified signal...
I have here my cmos rectifier circuit with RF input voltage equal to 0.25V and output rectified voltage equal to 25mV..
please help me find another cmos circuit architecture for rectifier that has high efficiency in rectifying RF signal :(
thanks in advance :)
Please help me find a efficient cmos rectifier circuit that operates at near to zero input voltage together with appropriate sizing of mos :)
i will really appreciate your help.
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