Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
thank U friend.if i see it in my exam i'll answer as U saied;
but i ask u something that is wrong with me.
what happens to out put if we disable the clock?
as i understand the output will not cange in mealy diagrams until the clock pulse edge;
i knew the answer is #4. but some one told me...
i have drew something wrong.
state D with 1/1 goes to state B. sorry. but nothing changes;
some thing is not clear sor me.
i think without Glitches #4.
#2 is with Glitches.
am I right?:?:
see w w w.seas.upenn.edu/~ese201/abel/abelMealy.html
if we don't use Glitches then it will be like moore.
thank u all
as i know mealy's out put can change with the change of asynchronus input(x)
i think if we connect the output to a register the #4 is correct
else
#2 is correct.
before the 5th clock we are in C state.
and in=1 out=0
in the 5th clock the input=1 and the state changes to D and we see...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
