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The sigal is stored on a capacitor. When it is reset, the switch on/off, I need to smooth the reset sigal to reduce charge feedthrough impact. Is there any good way to realize such circuit that it can generate a reset pulse with rise/fall time about 1us?
Thanks!
HI,nick
the photodiode I use is not the Si based, so there is no model for me and I need a equivalent circuit to approch its behavior, I only know the zero bias current and resistance,what should I do then?
thanks
spice modelling reverse biased photodiodes
hi Old Nick
picture (a) is the configuration and picture (b) is the equivalent circuit, the diode is modeled as a current source with its resistance and capacitance, the MOS is modeled as a VCCS, my goal is to decide the W/L of the MOS transistor...
reverse bias photodiode spice model
a photodiode is a part of active pixel sensor circuit, it can generate a current and inject into a MOS source, how can I model its resistance and capcitance, to set a appropriate voltage for MOS?
hi there,
Is BSIM3 model still accurate at cryogenic temperature(eg. 77K)?
I tried to figure out the low temperature IV characteristic with BSIM3 equation according to the foundary model. But the hand caculation result stoped at the instrinsic consentration, ni<0, superised! I ran a simulation...
about 90dB. That means my tran sim configuration is wrong?
If connect it as a source follower, the output surely follows the input, then it won't get a ramp figure, is my understanding right?
Hi, there
I am running a tran sim of an opamp in ADE, environment is set up as followed:
a small ac signal 100uV biased with a dc voltage is added at positive input, a same dc voltage is added at negative input. The single output's dc operating point is changing down slightly at the beginning of...
hi,sat
my av_extracted view only display metal layer without any poly or other layer, is that the same problem as saro? I will try your method tomorrow
hi,saro,
I do exactly as you said before,and still got the "r=NA" results in the schematic. IN the CIW, it promts me to run a dc sim and supply the path to results by set up the Parasitics. I tried run a dc sim in ADE from both schematic and av_extracted, but neither changed the show-up.
Thank...
assura parasitic extraction fracture
hi,guys
These days I am doing a layout of a cascode amp,I set up vdd and gnd as inputoutput pins and label them in the layout.After I run a rcx to extract the RC parasitics,backannotate in the schematic and find that, the pcapacitors are displayed without...
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