Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
thank you
let me clear my question once again
because of temp and volt the delay changes
is the amount of change same for two transistors having same width?
how transistor width is affected by pvt variations
if two transistors, which have different widths, is fabricated
both transistors are placed close to each other so process variation can be negletted.
voltage and temperature variations will affect the transistor in same way becuase they are...
thank you very much Mr Prashanthanilm.
can i have any theoretical proof or any article, journal or something which can be used as a reference ?
hope you will help me
at normal pvt conditions
two identical designs have same delay (same design i am duplicating)
the third one (which is different) is designed to get the same delay by changing the W/L ratio
at a different pvt condition
the delay will be different from the first pvt condition
but my...
thank you for the fast response Fahmy and Prashanthanilm.
let me clear once again.
i have 3 designs, two identical and one different . in the new pvt condition the delay will be different from the previous pvt condition. but in the new pvt condition what will be the delay of the three designs...
i have 2 designs of a logic(combinational) (for example 6T XOR and 16T XOR)
i am fabricating that in a chip. two identical 16T XOR and one 6T XOR. those are kept very near to each other in the layout. obviously the first two layouts are identical. same number of transistor, same W/L for...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
