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1. What will be the uncertainty value at the generated clock, will it remain same or more than the master.
2. What is the exact significance in "extra margin" in set_clock_uncertainty" (fairly confusing)?
sure to fix hold violation we add delay cell. but looking for some numbers.
and some more explanatory abt setup also.
example: I have a reg2reg hold is violated by -50ps in ff corner and the same path has the setup margin of +100ps in ss corner also suppose clock period of 1ns (with any...
example: I have a reg2reg hold is violated by -50ps in ff corner and the same path has the setup margin of +100ps in ss corner. (with any consideration of crosstalk analysis)
How to fix this?
during synthesis netlist compile convert dff to 625 dlat .and in ,lec l am using set_flatten -gated_clock, but all latch are unmapped points.
i am not able to understand why?
and which modelling i need to use.
please some body explain
i want to know that if suppose i found that there are 5 timing loops in my design by loop report. then how can trace the input and output of timing loos.
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