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Recent content by melonpy

  1. M

    Where find a good test code for test a 8051 core in fpga??

    Hi, I want to test my 8051 core(verilog) by fpga, and I want to find a good test program cover almost all function of 8051. Could you tell me where can I find it? Thanks
  2. M

    Automatic Generation of Synchronous Test Patterns

    Who have this paper???? Hi, if you have this paper, could you send me a piece. The paper is : Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits my email: melonpy@163.com
  3. M

    How DFT for a asynchronous circuit????

    If I have a block of asynchronous circuit in my design, and have synchronous circuit ,too. So how can I provide atpg pattern about asynchronous circuit by dft? SocBIST? Pls give me a detail description.thanks. :(
  4. M

    Who will do ATPG in Asic design team ?

    Re: ATPG ATPG pattern can be given after chip tapeout and befor mass pro. It's a relative independent step. But scan insertion, bist and boundary scan must be considered from start of project.
  5. M

    How to generate the tming model about analog design?

    STA: Static Timing Analysis For digital design timing analysis. For mixed-signal design, we should simulation whole chip include digital and analog design, so I want to generate timing model of analog design.
  6. M

    How to generate the tming model about analog design?

    generate timing model I want to generate timing model of analog design for STA timing analysis with digital design? Anyone know how?
  7. M

    2003 version about design compiler of synopsys.

    design compiler refrence manual: register retiming design compiler refrence manual: Optimization and Timing design compiler refrence manual: Constraints and Timing design compiler : Command-Line Interface Guide
  8. M

    who can tell me a link of library for desing compile ?thanks

    Re: who can tell me a link of library for desing compile ?th keep up
  9. M

    who can tell me a link of library for desing compile ?thanks

    Re: who can tell me a link of library for desing compile ?th keep up.
  10. M

    who can tell me a link of library for desing compile ?thanks

    Re: who can tell me a link of library for desing compile ?th design compiler user guide. I upload them for you, and these files is new for 2003 version. You can't excess into synopsys website if you have no account.
  11. M

    What value should I set on wire_load in .18 process(tsmc) ?

    Re: wire_load Can you give me more detail description about your question?
  12. M

    .13 vs .18 process - some ideas needed

    I dont't know if you use typical or fast model? For synthesis and timing optimizing, we should use slow model for better timing result.
  13. M

    Looking for resources on RF circuit layout

    Re: RF circuit layout? We have a project about RF circuit design( I mean RF IC design,not pcb). We must tape out this IC, so we must do backend layout. And I want to know some good experiences or suggestions about RF IC layout.
  14. M

    Code COverage and Regression Test Usage

    cadence cmview For soc verification, the most important thing of RTL simulation is code coverage. We must guarantee that ourRTL verification acquires higher code coverage.
  15. M

    A TCL script run in PrimeTime that help you trace your desig

    A good document about pt design
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