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Hello,
I am currently designing a LVDS standard interface to drive a Virtex-6 FPGA with 1.25Gbps (DDR) and I would like to know if the corresponding values for the input capacitance of the LVDS-pins in the data-sheet or IBIS-file are valid? With a normal LVDS interface (I=3.5 mA and Rd=100...
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