Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Duty cycle correction
Hi,
Do anyone have any paper regarding open loop duty cycle correction block. I read a paper which talks about delaying the clock input and then having an interpolator to get 50% duty cycle. (Paper - Open-loop full-digital duty cycle correction circuit - C. Yoo, C. Jeong...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.