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illegal left hand side of continuous assign
Hi all,
I am using Verilog to design a system.
But there is an error in my code.
//--------------------------the error info------------------------------
"Register is illegal in left-hand side of continuous assignment"...
verilog trigger
Hi all,
I want to design a signal that can trigger by using rising edge and falling edge by
using Verilog and download it into FPGA by using Quartus.
for example:
//--------------------------------------------------------
always_ff @(posedge DF_CLK, posedge seen)
begin...
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