Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Latency is the amount of time lapsed between input applied and meaningful output received. It is not directly related to frequency. Latency is determined by the number of stages between input and output.
Frequency is determined by the critical path delay ie the delay of the longest path...
Synthesis
Architecture is a very generic word. Answer is yes and no. Synthesis works on RTL and not architecture.
RTL synthesis will not change the registers and hierarchy (unless you flatten it) .
But it may change the combinational logic and the FSM encoding.
Architecture must be described...
Can you provide more details like what sort of ARM code you have (HDL or SystemC).
Co-simulation may be a tricky task. You may require memory, bus model etc. But I think in modelsim you can co-simulate systemc and HDL models.
A pin of a gate is driving say 100 inputs of other gates. (eg net going from output of a nand gate to select pin of 100 muxes).
Proper buffering takes place during PnR. In pre layout STA, this pin will have a high transition and consequently high delay. This leads to timing violations.
Can...
primetime .lib files
Primetime:
For libraries is it possible to link in .lib format instead of .db format?
e.g.
link_path mylib.lib
link_design
pt gives an error: "Not in DB format (DB-1) "
My question is whether a .db format is always required? OR .lib format is also acceptable?
thanks...
hdlin_preserve_sequential
I have a module with some sequential elements. During actual module usage the path through sequential elements is never exercised.
I want to remove flip flops during synthesis. I tried using set_case_analysis and putting mux select and clock value to 0. But dc still...
Putting the timing constraint as 1.8 ns I did synthesis and PnR. the Design Compiler, Encounter successfully did SPnR. There are no violation in Primetime reports.
But when I run my post synthesis design in modelsim at this clock period, I get $ recovery errors. I can only run my design at 2.4...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
