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For CS4340, while power-up, reset or incorrect clocks, the mute control pin (pin 16) goes high. This could be a way to check if the data sent from CPLD to DAC is correct.
In my opinoin, MCLK, SCLK, FSCLK should always be stable. All you need to do is keep the correct output sound and mute the...
bypass cpld
Hi,
I try to give some simple suggestions, maybe you already know that:
1. Make sure the CS5333/CS4340 are configured in the right way. This means you should check if the settings for both ADC/DAC ("sample rate", "digital interface format", "clock mode" ...etc) are correct. For...
ISE 4.2i/5.1i installation
Hi:
I encountered great difficulties in installing ISE 4.2i/5.1i and spent a lot of
time to solve the problems. I hope my experiences do help those who want to
learn Xilinx ISE 4.2i/5.1i but fail to install it.
The supported O.S. platform is:
ISE 4.2i -- for...
I prefer TMS320C5510 DSP Starter Kit (DSK) (DSP8923U) ,
Embedded JTAG support via USB
High-quality 24-bit stereo codec
256K words of Flash and 8 MB SDRAM
Include Code Composer Studio for DSK
It's powerful,too.
Furthermore, it's cheap! (usd$ 399)
mp3 decoder vhdl
I guess it is difficult to implement MP3 encoder/decoder on FPGA.
The polyphase filter bank and psychoacoustic model causes a large amount of computation and table look-up. Those are better done by a MCU or DSP,such as ARM7 or TI 55xx DSP.
Any other suggestion?
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