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Recent content by mark_nctu

  1. M

    how to test the PSRR of the class d Amplifier?

    how to measure psrr class d amplifiers Hi renwl : We can't find in AP manul.
  2. M

    Need your help, I want to start learn class-d amplifier

    Thanks for your sharing!
  3. M

    How to improve LDO's transient response?

    transient response of ldo Maybe you need a large external Capacitor to imrpove tansient response!
  4. M

    challenging design of bandgap reference circuit

    vdd referenced gnd referenced circuit FYR!
  5. M

    The wide dynamic input voltage of low drop-out regulator

    Try to design internal a low voltage regulator for bandgap circuit. It will improve line regulation.
  6. M

    How to deal with the high input voltage of LDO

    Is the process only has 1.8V desice ?
  7. M

    design a low power and low process variation ring oscillator

    How to design a low power and low process variation ring oscillator? :!:
  8. M

    Class AB Audio Amp. THD+N

    Dear All: I design a Class AB Audio Amplifier. It has poor THD+N(-50dB,RL=8Ohm) when Pout=1mW. How to improve THD+N when low output signal ? Thanks! :D
  9. M

    What's the problem of Bandgap?

    Check circuit's control loop phase margin!
  10. M

    Class AB OPA AC Analysis ??

    I try smash to simulate the circuit and get the same result. But change other fundry's spice model, the phase is ok at Vdd=5V. We can be sure that circuit is stable at step input. Maybe the circuit is ok. Thanks.
  11. M

    Class AB OPA AC Analysis ??

    Hi xjxmn: I use Hspice to simulate the circuit. Thanks for you suggestion. I will try any other vonder's spice simulation tool.
  12. M

    Class AB OPA AC Analysis ??

    Hi walker5678: VOP is used to sense OPA power current. So VOP si DC =0 .
  13. M

    Class AB OPA AC Analysis ??

    LDC=CDC=1000 Added after 3 minutes: Hi walker5678: Step input is stable. I try your structure. The curve is the same.
  14. M

    Class AB OPA AC Analysis ??

    I design OPA with OTA + Class AB output. When OPA at Vdd=5V , Phase has inverted to 180. But low vdd (3V) is ok. Could some tell me how to solve the problem? Circuit: Test_Circuit: 5V AC Result: 3V AC Result: Added after 2 minutes: Sorry Reupload 3V AC Result:
  15. M

    Design big delay element

    You can use curent to generate a small current source and chagre a mos to make the large delay time.
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