Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I have a setup violation in the reg to output paths. When i tried to debug these paths, i found that clock network delay for the capture clcok is zero.
So, i think that i have a problem with the clock latency, and i am confused about how can i specify the proper clock latency, and is this in...
Hi,
I replaced these two lines with the following lines. It gives me no warning messages, but I am not sure if this is the best solution.
set f [all_inputs]
set a [get_ports $all_clock_ports]
set b [get_ports $obi_input_ports]
set c [get_ports $irq_input_ports]
set d [get_ports...
Hi,
I have a problem regarding the constraints file.
DC compiler gives me warnings regarding these two lines in my constraint file:
set all_other_input_ports [remove_from_collection [all_inputs] [get_ports [list $all_clock_ports $obi_input_ports $irq_input_ports $early_input_ports]]]
set...
Hi,
I am trying to run a timing analysis in prime time, but it gives me these errors?
Error: Could not resolve net 'id_stage_i/register_file_i/N821'. (PARA-075)
Error: Could not resolve net 'id_stage_i/register_file_i/n579'. (PARA-075)
Error: Could not resolve net...
Hi,
I have an error when using route_group command in the last part in the script of the CTS part
And I have searched for long time for the meaning of this error but i found nothing, could you help me?
icc_shell> route_group -all_clock_nets
INFO: CapModel...
Hi,
I have a problem with the topographical flow.
After reading the resultant ddc file from DC-topo in ICC, the place_opt -spg command gives me this error.
So, I don't know what is missing and what causes this error?
Thanks,
icc_shell> place_opt -spg
Error: Design does not have Physical...
Hi,
I have a problem reading the floorplan file in ICC.
When I write the read_floorplan command in ICC to read the resultant floorplan file from DC-topo, it gives me many errors regarding the VDD and VSS nets.
I attached below the last error lines in the result of command read_floorplan...
Hi,
I have a problem regarding the power planning step.
When I check the connectivity of the net after the power planning stage, I find that the design is open and all nets are floating.
So, can anyone tell me what is missing in the power planning stage and what causes this error?
I attached...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
