Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by manili

  1. M

    3D IC Design: Is it possible to stack CPU and FPGA?

    Thanks a lot Andre. I liked the way you replied, so I marked it as the solution/answer. Are there any resources that I can know more about constraints of 3D-IC designing in real world (I am not looking for academic level info and papers)?
  2. M

    3D IC Design: Is it possible to stack CPU and FPGA?

    Thanks Dick, I appreciate your time to reply but did not find what I was actually looking for, yet. It's not about me, it's about multi-billion dollar R&D teams at Intel and AMD. Is designing such 3D-ICs that impossible for these guys?!
  3. M

    3D IC Design: Is it possible to stack CPU and FPGA?

    Hi all, Heterogenous architecture is nothing new at all. We have Zynq family (ARM + Xilinx FPGA), we have Intel's Xeon Scalable processor with FPGA integrated, we have OSFPGA and Caravel in the open-source ecosystem and other SoCs like these. But AFAIK none of these SoCs are using 3D-IC...
  4. M

    [SOLVED] Design an RTL for different FPGA types compliance

    Thanks for your reply @TrickyDicky: So that's why we have to add many changes to almost every single IP core hosted by the OpenCores website?
  5. M

    [SOLVED] Design an RTL for different FPGA types compliance

    Hello all, I'm wondering to know if it is possible to design an RTL which is acceptable for different types of FPGAs (excluding the resource volume restrictions)? For example, What would happen if I do not use any sorts of hard-cores and soft-cores? Now, is it possible to synthesize my RTL for...
  6. M

    [SOLVED] Is there a way to change default programmer port?

    Dear niciki, I marked the thread as "Solved". I didn't notice the button. Sorry!
  7. M

    [SOLVED] Is there a way to change default programmer port?

    Thanks a lot. I didn't find it anywhere else.
  8. M

    [SOLVED] HSPICE 2013 SP2 28T Full Adder Simulation Problem

    That was awesome!!! You just solved my problem. Thanks a lot :)) Do you have any ideas why I'm getting negative output (about micro volts) sometimes? Is it OK?
  9. M

    [SOLVED] HSPICE 2013 SP2 28T Full Adder Simulation Problem

    I added the schematic in the attachment. Thanks.
  10. M

    [SOLVED] HSPICE 2013 SP2 28T Full Adder Simulation Problem

    @andre_teprom, Thanks a lot for the reply. Unfortunately I'm implementing the circuit fully in HSPICE (for learning purposes). I don't know if there is a tool to convert HSPICE to schematic or vice versa?
  11. M

    [SOLVED] HSPICE 2013 SP2 28T Full Adder Simulation Problem

    Hi all, I'm trying to simulate a 28 Transistor CMOS Full Adder using HSPICE 2013 SP2. Here is the picture of what I'm trying to implement. This is my HSPICE code: CMOS Full Adder .include '../32nm_LP.pm' .temp 25 .param tech_lngth=32n .param vmax=0.9 .param wnmos=64n .param...
  12. M

    [SOLVED] Is there a way to change default programmer port?

    Hi all, I'm trying to program my ZCU104 evaluation kit using a SmartLynq programmer. I'm wondering to know if there is a way to change the default port (i.e. 3121) from Vivado 2018.1 Suite or somewhere else? Is it possible to do so for the onboard JTAG programmer? Thanks a lot. Mohammad
  13. M

    What's going on behind FPGA-based Clouds?

    I used laughing smily because you used that emoji and thought you were just kidding like the emoji said, sorry about misunderstanding ... BTW how can I defend myself when you judge me before hearing my answers?! Thank you and wish you all the best.
  14. M

    What's going on behind FPGA-based Clouds?

    Well, great costly suggestion :laugh:. However I already got the answer from the Xilinx forum: http://forums.xilinx.com/t5/SDAccel/What-s-going-on-behind-the-AWS-EC2-F1-FPGA-accelerated-cloud/m-p/838151 BTW thanks a lot.
  15. M

    What's going on behind FPGA-based Clouds?

    Hi every one, I don't know if this is a good place to ask such question or not, but it's my last hope to find the answer. These days we see a lot of cloud service companies (like Amazon) are providing their customers with a new service called FPGA-based cloud. I want to know what's happening...
See more

Part and Inventory Search

Back
Top