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Recent content by manchuk

  1. M

    Pulse Clock Constraints

    I have 3 clocks in my design. The third pulse clock is generated based on first clock.What is the best to represent this third pulse clock. CLK1 and CLK2(duty cycle of 48%) are non overlapping phase clocks CLK3 is a pulse clock that is double the frequency of CLK1 but has 23% duty cycle. The...
  2. M

    Formality - Synchronizers causing a problem

    @rca : I am quite new to formality. How can we provide the second input to formality ?
  3. M

    Formality - Synchronizers causing a problem

    I have 2 synchronizers in my design. Formality is not able to recognize them . Formality failing points show D and stage1_sync. But stage2_sync passes. The sample RTL code is below reg stage1_sync, stage2_sync; assign Q = stage2_sync; always @(posedge CP or negedge CL)...
  4. M

    ICC - Routing Blockage issue

    Thanks a lot dkpang. I tried this command but sadly it didnt create the routing blockage.I am not sure whats going wrong :(.
  5. M

    ICC - Routing Blockage issue

    I want to create a rectangular routing blockage and a placement blockage in my design. I am trying to use the following commands in the preplacement script for creating a routing blockage of all metal layers and all vias but the Tool still routes in that area . create_routing_blockage...
  6. M

    ICC - SNPS_LOGIC nets

    @randyest..thanks for the reply. There is a command to remove the tieoff cells. Would you be knowing the implications of using that ?
  7. M

    ICC - SNPS_LOGIC nets

    IC Compiler inserts some SNPS_LOGIC0 and LOGIC1 nets. I am not sure why they are inserted. What is its significance. How can I eliminate or rename them ?
  8. M

    Create a case insensitive netlist from verilog using DC

    @RBB..Thanks for the reply. This netlist gets ported to another tool which is case in sensitive. The tool will choke if there are 2 module names like TOP_module1 and top_module1. So I am trying to force DC to dump out a case insensitive netlist .
  9. M

    Create a case insensitive netlist from verilog using DC

    @randyest : Thanks a lot for the perl one liner .My only concern is if the design has one net name TOP_name and a different net name top_name. When I run this perl scrip it will short 2 nets which are supposed to be different. TOP_name and top_name are supposed to be 2 different nets.I am not...
  10. M

    Create a case insensitive netlist from verilog using DC

    I am new to Synopsys design compiler. Trying to synthesis a verilog code to create a case insensitive netlist. The verilog code has some uppercase parameters like NAME, DATE etc . These parameters are synthesised into the gate names like top_NAME top_DATE . I would like to get all lower case...
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