Create a case insensitive netlist from verilog using DC

[manchuk]

I am new to Synopsys design compiler. Trying to synthesis a verilog code to create a case insensitive netlist.
The verilog code has some uppercase parameters like NAME, DATE etc . These parameters are synthesised into the gate names like top_NAME top_DATE . I would like to get all lower case netlist with names like top_name or top_date.

I am using the commands

define_name_rules LOWERCASEONLY -allow "a-z 0-9 _"
change_names -rules LOWERCASEONLY -verbose -hier

These commands dont change the upper case parameters in HDL to lower case names in netlist. I would like to know if DC command can change the uppercase RTL names into lower case netlist during synthesis ?

 

[randyest]

I'm sure there's a way to do that in DC, but I can guarantee it will be faster and easier to do it with perl with a simple one-liner like:

perl -p -e 'tr/A-Z/a-z/;' input_file > output_file

 

[RBB]

define_name_rules MIZA -case_insensitive
change_names -rules verilog -hierarchy
change_names -rules MIZA -hierarchy

 

[manchuk]

@randyest : Thanks a lot for the perl one liner .My only concern is if the design has one net name TOP_name and a different net name top_name. When I run this perl scrip it will short 2 nets which are supposed to be different. TOP_name and top_name are supposed to be 2 different nets.I am not sure if DC will assign such names but incase it does then it will break the design.

@RBB : Thanks for the commands but for some reason this changes the net names but not the module instance names in netlist . The module names are still of the format TOP_name (combination of upper case and lower case).

Would we be having any command or switch that will give all lower case module instance names in the created netlist ? Thanks in advance.

 

[RBB]

I didn't read your original post closely enough. It should be easy enough in a tcl script to get each module name and rename it to it's lower case equivalent though.

Out of curiosity why is it so important to have a case-insensitive netlist? All down stream tools I've used handled DC netlists just fine.

 

[manchuk]

@RBB..Thanks for the reply. This netlist gets ported to another tool which is case in sensitive. The tool will choke if there are 2 module names like TOP_module1 and top_module1. So I am trying to force DC to dump out a case insensitive netlist .