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Hi all,
I have coded a parameterized module in verilog. In this module, one particular parameter configuration leads to an illegal port width which looks like this: reg [-1:0] my_data; and I was surprised to find that VCS didn't flag any error or warning for this. :shock: Functionally, the...
Sorry... my reply was complete nonsense.. :( didnt give much thought.
The two replies above are correct.. U don't need a clock to read FF o/p. They are always ON.
You can put a mux in the clock path of a simple register like this:
CLK = (READ . CLK_RD) + (WRITE . CLK_WR)
where READ and WRITE are active-high read/write signals for reading data from this register, and CLK_RD & CLK_WR are the 2MHz & 25MHz clocks respectively. CLK will be the wire that is...
@ templemark
Hi.. thanks for replying.
What I understood from ur reply is that SOC (start of conversion) pin is used to provide 'sort of' clock pulses to the DAC (and these pulses initiate the data conversion).
Right now, various blocks in my DAC design work w.r.t a clock signal. At the...
You can feed each of the 16 outputs from decoder to the Clock input of 16 individual T-FlipFlops (positive edge-triggered). Connect all T-inputs to '1' (Vdd) permanently.
When any of the decoder outputs goes 0 -> 1, the bit in the T flip-flop will toggle (assume it is '0' initially).
Now, for...
I am designing an 8-bit capacitor DAC (thermometer coded).
I am confused about the clocking in the DAC. I have gone through several datasheets and I didn't find the CLK pin on any DAC chip!! They just have supply pins, input-pins, output, and Vref. Then what about CLK signal? Are the clocks...
You are mixing up Structural coding style inside Behavioral. You can't instantiate a module INSIDE conditional statement as far as i know. It has to be done outside the IF statement.
Can you elaborate in more detail.. what functionality do you want to achieve?
Hi guys,
I've to start working with PureSpec USB VIP (from Denali) but the user guide is too complicated for me. Can anyone suggest a better manual.
As I told I'm a beginner. Any help is welcome!
Well, as u might be knowing that in today's VLSI design, the sub-threshold current becomes the one of the major factors of the power consumption, especially when u design a memory chip.
Here's some extract I found in one such project report online...
To reduce the leakage power in the SRAM...
hi yaju
i think I2C, SRAM design r indeed good ideas..
ask anoop.. he has some material on "SRAM Cells with sleepy transistors"
--- Vicky here! all d best :)
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