Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by mahdinov

  1. M

    can you explain to me the behavior of isolation cell?

    but i don't have a Corporate Email so i can't download it.
  2. M

    can you explain to me the behavior of isolation cell?

    hi denki23, i need the LPPM book for low power, if you can send it to me plz.
  3. M

    Looking for a document with UPF examples

    hi, Unified power format is a standart which describe the power intent of a design. I found the user guide of the standart and i understood the commands, but i found a lot of difficulties in writing a program, so i need a document which contains examples with solutions in order to see hwo we...
  4. M

    can you explain to me the behavior of isolation cell?

    thank's friends but why isolation cells clamp the output node to a known voltage also what's the role of the enable input?
  5. M

    can you explain to me the behavior of isolation cell?

    isolation cell can you explain to me the behavior of this cell?
  6. M

    low power technics in rtl synthesis

    thank's a lot for your help, can you send me plz some of these documentation because i didn't find what i want in the net.
  7. M

    low power technics in rtl synthesis

    hi, i actually prepare my these in STericsson company, and my subject is low power technics in rtl synthesis and i am in aa step of documentation. I didn't understand the clock gating method, so i ask you to help me, also i hope you tell me if they are other methods of reducing power in...

Part and Inventory Search

Back
Top