low power technics in rtl synthesis

[mahdinov]

hi,

i actually prepare my these in STericsson company, and my subject is low power technics in rtl synthesis and i am in aa step of documentation.
I didn't understand the clock gating method, so i ask you to help me, also i hope you tell me if they are other methods of reducing power in digital design.
even if you have documentations, send it to me plz

i will be very gratful

 

[johanlo]

Verilog flip-flop:

reg d;
wire load, value;

always @(posedge clk)
begin
if (load)
begin
d<=value;
end
end

The flop will be loaded at rising edge when load is 1. Without clock gating this will ble implemented as a 2-1 mux in front of the flop. The load signal chooses if d (fed back) or value is to be stored in the flop.

With clockgating the mux is replaced with a clock gate. load will controll the clock into the flop. If load is high, value is stored in the flop. If flop is low, the clocked is stopped and nothing is loaded.

 

[ljxpjpjljx]

lower power domain should use specific tools? right?

 

[xinsu]

you can reference low power constraint CPF(cadence) or UPF(synopsys) documentation.

 

[mahdinov]

thank's a lot for your help, can you send me plz some of these documentation because i didn't find what i want in the net.

 

[rama_bing]

Hi,
you can get UPF documentation from the following link
http://www.accellera.org/activities/p1801_upf
for upf topics:
http://synopsysoc.org/magicbluesmoke/