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Recent content by maharaja1989nellai

  1. M

    how to do simulation

    Analog Design of CMOS Integrated Circuits by Behzad Razavi, CMOS circuit design,Layout and Simulation by R. Jacob Baker etc thanks
  2. M

    Control voltage variation in PLL

    thank you AdvaRes
  3. M

    Control voltage variation in PLL

    i set my loop capacitor filter are within the Bandwidth limit(bandwidth=Reference frequency/10)...I need my PLL control variation will be uV range.. thanks
  4. M

    Control voltage variation in PLL

    Hi all, iam finished my PLL inCP90nm.After locking my PLL the control voltage variation will be 6mV...After adding Decoupling capacitor(Decap=150p) between supply and ground the control voltage variation will be reduced to3.5mV... my questions are 1) How much value of control...
  5. M

    VCO waveform and phase noise

    Hi.. if u want to find the values of phase noise of VCO you must run PSS analysis and phase noise analysis together..
  6. M

    PLL control voltage variation

    HI..Wim... thanks for ur reply...
  7. M

    PLL control voltage variation

    Hi... everyone....how to reduce the control voltage variation in PLL in uV range? In my PLL iam adjusted loop parameters and chargepump current so many ways..But i can't get control voltage variation in uV range.. thanks all......
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