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hey thanks for replying
actually i am using the concept of parallel multiplication in which in each cycle one row of a matrix is multiplied with each column of the second matrix....so in next cycle the next row with all the columns of the second matrix thus it reduces the computation...
It's very simple
you'r data type in the rom module is
read_en ---- input wire type
address ---- input wire type
Q ---- output reg type
now to instantiate this module in top module declare
read_en as reg or wire type
address as reg or wire type
Q as wire type
(all the variables with same...
hey
I am a student of B-tech . I am doing a project in which i have to use a parallel multiplier. I have to multiply two matrices of 8x8 size and each element is a 16 bit fractional number represented in binary format. I wrote a code in matlab and verilog both but when I matched the result of...
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