Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by luqman_abbas2

  1. L

    Using PHY MII in verilog!

    Expected Output: "55 55 55 55 55 55 55 5D 06 05 04 03 02 01 FF FF FF FF FF FF 08 00 45 00 00 36 00 00 00 00 80 11 B9 4A C0 A8 00 08 C0 A8 00 14 1F 90 1F 90 00 22 4C 3E 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 20 20 21 22 23 24 25 00 00" While what I am getting these nibbles for the...
  2. L

    Using PHY MII in verilog!

    Hi All! I am trying Ethernet MAC PHY MII on spartan3e1600e development kit. I have made a very simple receiver logic in verilog which simply works on rx_clk (2.5 MHz in my case since i am working on 10mbps) and rx_dv signal to display the received data nibble by nibble on the output. The...
  3. L

    Help Required on Developing ethernet MAC on FPGA.

    Okay i will get back soon. Regards!
  4. L

    Help Required on Developing ethernet MAC on FPGA.

    Hi All! I am intermediate to FPGA. and working on development of Ethernet Controller Using hard wire Logic on Spartan 3e 1600 Kit. I have managed Ethernet transmitter (as given on https://www.fpga4fun.com/10BASE-T0.html ) to get working. but i am stuck in development of receiver side. as the...
  5. L

    [SOLVED] Cheap PCI FPGA boards.

    Thanks for replying. I have to work on PCI. Regards. - - - Updated - - - One thing more please tell me are there any demo examples available with the suggested board so that i can practice it over to make my desired design? Regards
  6. L

    [SOLVED] Cheap PCI FPGA boards.

    Hi ALL! I am assigned to make a protoype for FPGA- pC communication via PCI. I am looking for cheap FPGA boards (upto £120). to start my development. ANY suggestions regarding. Regards
  7. L

    [SOLVED] NIC teaming solution (HW/SW)

    @moottii I am looking to associate three different windows embedded type hardware systems via ethernet. and i need redundancy via teaming. Regards
  8. L

    [SOLVED] NIC teaming solution (HW/SW)

    Hi All! I am required to figure out a solution for NIC teaming for fail over scenario! I have two queries - how can i team two NICs in a non server OS.(any software available commercially) - If i have only NIC in my PC is there external hardware available...
  9. L

    adding customized FIFO peripheral (in verilog ) to Microblaze.

    hello! I am trying to add a FIFO custom peripheral with some additional code in micro Blaze. I a " " i have tried the solution in http://forums.xilinx.com/t5/Embedded-Development-Tools/ERROR-NgdBuild-604-in-XPS-12-4/td-p/203867 but i m not getting results.. any one can help me out...
  10. L

    Does an FPGA need an external clock source?

    well dear! the FPGA generally doesnot need clock source for combinational logic. The need of clock is application specific e.g sequential logic etc. USART will be needing the sync pulse (either generated by PLL or board clock).. Regards
  11. L

    adding customized FIFO peripheral (in verilog ) to Microblaze.

    Hi all! I am trying to interface a FIFO customized peripheral to MicroBlaze in Verilog because I do not know VHDL. I have got through the stuff available and tried some of them too on my Spartan3e 500 kit. but i am unable to acquire good results. any guidance for me?? Thanks in advance! Luqman
  12. L

    [SOLVED] UDP Communication through FPGA

    Well folks Thanks for directing me help in my stuff!
  13. L

    [SOLVED] UDP Communication through FPGA

    hey guys I have a had some feeling that the FCS calculation of my formed packet my be wrong. thats why my packet is discarded by NIC. https://ask.wireshark.org/questions/7549/if-fcs-is-wrong-will-wireshark-detect-this-fact-how-can-i-see-it so how can i correct my CRC(FCS) as it is appended by...
  14. L

    [SOLVED] UDP Communication through FPGA

    i have tried with giving MAC address of nic as dst. MAC as address the results are same. and i hven't setted any filtering options in wireshark!
  15. L

    [SOLVED] UDP Communication through FPGA

    FF FF FF FF FF FF 06 05 04 03 02 01 08 00 45 00 00 2E 00 00 00 00 80 11 B9 6B C0 A8 00 01 C0 A8 00 02 1F 90 1F 90 00 1A DE DD 12 34 56 78 90 11 22 33 44 55 66 77 88 99 00 11 12 00 when i put the highlighted 2 bytes in packet the wireshark donot gather the packet if i put 0x0000 wireshark says...

Part and Inventory Search

Back
Top