Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by longqingshan

  1. L

    Resistance Flicker Noise Question

    Hi, In Veriloga, resistor flicker noise is modeled with a noisy current source: "I(p, n) <+ flicker_noise(kf*pow(abs(i_r), af)/geo ,ef, "flicker")"; In spectre, resistor flicker noise is modeled by parameter AF,EF.... I think two methods should be agreed with each other, but apparently...
  2. L

    help me about ESD protection system

    thanks for reply! I viewed some IO pads in the TSMC standard IO libaray, I found the ESD MOS drawed in finger-style,and the minimum distance between pickup and drain is 1.624um.so is the parasitic resister in series with DN(or DP) a problem to discharge the ESD current?
  3. L

    help me about ESD protection system

    I have a doubt about ESD protection system showed in FIG. There are two ESD current flow paths in PS and ND mode. For instance, for PS mode, the ESD current can flow through DP to VDD, and then through power clamp to VSS. The ESD current can also directly flow through MN’s parasitical NPN...
  4. L

    [SOLVED] I am confued at calculating total power of 1/f noise

    The integrated 1/f noise is proportional to ln(fh/fl), where fl is the lower limit for integration, and fh is the upper limit. So,for real application,how to determine fl?
  5. L

    question about sigma_delta adc decimation fiter

    Thanks FvM! Added after 4 seconds: Thanks FvM! Added after 8 seconds: Thanks FvM!
  6. L

    question about sigma_delta adc decimation fiter

    adc decimation when using the cic filter as decimation filter,is a compesation filter needed? the basic cic structure is composed of two section,integrator section and comb section.I found that the response of integrators for dc input is without bound. so does that imply we can not use the...
  7. L

    help- about lee's rule for sigma-delta modulator stability

    I do not understand how lee's rule was derivated? can anyone help or pass me some materials? thanks!
  8. L

    a question about quantilation noise in SDM.

    Why quantilation noise power just folds in frequece band -fs/2~+fs/2?
  9. L

    a doubt about hspice relative tolarence

    hi , i want to know hou relative tolarence effects convergence. i just know if delta F(x) <absolute tolarence ,equation converge.dose relative tolarence contributing to convergence have relation to slope of F(x) at F(x)=0?
  10. L

    a doubt about hspice relative tolarence

    hi , i want to know hou relative tolarence effects convergence. i just know if delta F(x) <absolute tolarence ,equation converge.dose relative tolarence contributing to convergence have relation to slope of F(x) at F(x)=0?
  11. L

    a doubt about oscillator's start_up

    thanks everyone! I set .tran 1p 1ms,It starts oscillation.
  12. L

    a doubt about oscillator's start_up

    when i give a initial current in the conductor, the similar thing occurs.my teacher told me if oscilltotion happens,that's ok! is that beacause of accuration of hspice?
  13. L

    a doubt about oscillator's start_up

    hi, i used an cmos amplify as gain stage for a pierce oscillator.at the oscillation frequece,the phase shift of LCR network is larger than 1.when i add a large current pulse at the terminal of L,it start to oscillate with magnitude growing.But i find magnitude decreased even stop oscillation...

Part and Inventory Search

Back
Top