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Hi friends
i have the following questions. Thanks in advance for answering.
1. How PT calculates setup and hold time between 2 FF clocked by two different clocks?
2. When we use set_max_delay and set_min_delay , the delay calculated by the PT is over ridden, so what will happen to the data...
Hi
i have a question on timing constraints
1. How will find out the setup and hold time of a FF before hand?
2. How I know that multi cycle path exist between two FFs?
3. How to find Clock frequency at which the code/module works ( i know that the clock frequency will be decided, but let say i...
is it possible?
Dear friend
for my project i need a LCD monitor and an audio output.
is it a wise decission to use µc for this project.please suggest me.
regards
lokesh
Re: cycle steeling
Dear friends
I hope my question was not clear
This particular topic i asked is regarding the static timing analysis using prime time
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