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Recent content by logari84

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    Advice on usage of Altera FFT IP core

    Hi, I have a data set with timestamps of detected events (e.g 14.2, 14.3, ... 15.2 in seconds but with precision in ns time scale). The detection follows a periodic form. So, I need to find the frequency and consequently the period of the signal (about 695ns). I used python and Fourier...
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    [SOLVED] SystemVerilog, "struct packed", module mapping issue in Encounter RTL compiler

    SystemVerilog, "struct packed", module mapping issue in Encounter RTL compiler Hi all, I am trying to synthesize a design with Encounter RTL but I am having problems with a struct. I am using many structs so I am posting only one as an example. Let's say I am using this which is...
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    [SOLVED] SystemVerilog access members of multidimensional array of struct

    Anyway. I was looking for a "smart" fast way. In the end I used generate to make the instances of my module.
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    [SOLVED] SystemVerilog access members of multidimensional array of struct

    Hi all, I will try to explain what my question is. To make it more clear lets make an example. I have the struct: typedef struct packed{ logic[`PR_ADDRESS_WIDTH-1:0] address; logic[`ADC_CODE_WIDTH-1:0] adc0_code; logic[`ADC_CODE_WIDTH-1:0] adc1_code; logic[`ADC_CODE_WIDTH-1:0] adc2_code...
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    SystemVerilog assign value to signal

    Hi, I am quite new to SystemVerilog. I want to assign a value to a signal that has a width set by a parameter (CODE_WIDTH). When trying to compile in ModelSim I get the error: near "'b": syntax error, unexpected BASE, expecting ';' or ',' The line is: assign memory_code[02] =...
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    [SOLVED] Having trouble accessing all files in folder using VHDL textio library

    Re: Accesing all files in folder using VHDL textio library Thank you very much. I don't actually understand what .all at fname.all does. But I managed to make it work. I didn't know that you can create one continuous string by concatenating some others. That, plus the integer'image() was the...
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    [SOLVED] Having trouble accessing all files in folder using VHDL textio library

    Accesing all files in folder using VHDL textio library Hi all, for the project I am currently working on, I am using data from an input file. My design is almost done but I have tested it only with one input data file. Now I want to test it on all of the data files (~10000). In addition I want...
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    SystemVerilog FIFO implementation

    Nice feedback 'ads-ee'. In my design I have all the parameters in a separate file. I use the defines just for the simulation. This is actually a sample code for the logic of the FIFO. I usually work with VHDL so whenever I want to use a component that is generic I just use a tool to produce it...
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    SystemVerilog FIFO implementation

    I joined the forum quite recently and I don't know how things work. I just pushed the "attachments" button when I was composing the original post. Then a pop-up window appeared and I tried to upload files from there. I don't know if this is what you mean. :)
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    SystemVerilog FIFO implementation

    Hi all. I've been looking for a FIFO implementation in SystemVerilog and unfortunately I couldn't find anything. So I decided to make one and post it here just in case someone needs it in the future...
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    [SOLVED] SystemVerilog file IO operations

    My bad. It wasn't an error but a warning. Probably cause of bad call of the function. Haven't explored $fwrite() in details yet. I will do when I need it :) . But now I think I got the point of how it works. Thank you for your help.
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    [SOLVED] SystemVerilog file IO operations

    Thank you for your fast reply. I've already checked this link, but can't tell if it's for SystemVerilog or Verilog. At some point I get some compilation errors when I try to use stuff from Verilog. I am very fresh to both languages and can't easily distinguish what is used in one and what in the...
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    [SOLVED] SystemVerilog file IO operations

    Hi all, I am struggling to find some documentation for file IO operations in SystemVerilog. I can't find a decent guide even for Verilog. I managed to read a file or write to a new one, but I managed to do only the very basic operation (read and write as char). What I actually need is to read...
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