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Recent content by lnuhcs

  1. L

    In Encounter DEV RPT,what's the difference between real error and total error?

    hi, i'm confused with the differences between "Real DRV error " and "Total DRV error" in encounter 8.1.can any one give some explainations ? thanks in advance.
  2. L

    Some one who can tell me what's the advantage of AHB bus to wishbone.

    ah......I cant open that website for some reasons.can you copy what Rudolph Usselmann said ? Or send the short document to my email ? My email is hu_cs@hotmail.com . Thanks alot. *** Bless YOU!
  3. L

    Some one who can tell me what's the advantage of AHB bus to wishbone.

    Always AHB bus is used in advanced soc core,but what is the advantage of it?
  4. L

    what the else function of sel_o in wishbone?

    In a wishbone soc platform,the bus is 32 bits,but some state or control registers in some slave IP is 8bits.In this cases ,a signal SEL_O is always used to choose which byte is selected on the bus.My question is ,How Does CPU dual this selc_o signal and the register address.Does sel_o and...
  5. L

    When CPU achieve date from mem.Does the address of the memory always multiple of 4?.

    Thanks for your explain,and if the last two bits of the address always been wasted,what's the sense of it still exist in the SOC system ? MY BEST REGARDS! ---------- Post added at 09:06 ---------- Previous post was at 08:50 ---------- In a wishbone soc platform,the bus is 32 bits,but some...
  6. L

    When CPU achieve date from mem.Does the address of the memory always multiple of 4?.

    If it is ,How does CPU get the data that the address is not multiple of 4,and if it is ,the last two bits of address should always be 2'b00,Does CPU waste the two bits of address?\[\displaystyle\]
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