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Recent content by ljxpjpjljx

  1. L

    What is verification IP and how is it different from ASIC?

    Now cadence or mentor will provide VIP (HDMI,AXI,SPI.......) for you to verify your IP more efficiently, this VIP usually are written with SV or E!
  2. L

    Functional Coverage in vcsi...

    first you should add functional coverage with SV code in your testbench and run simulation with -sv option!
  3. L

    difference in running cadence simulation

    usually now we use irun command is more efficient!
  4. L

    [MOVED]VLSI industries in Kolkata

    Re: VLSI industries in Kolkata also can anyone share the IC company in Toronto?
  5. L

    Verilog - netlist Error

    have you checked whether A and Y is 1 bit width or 3 bit width?
  6. L

    ius,irun,ncsim,gcc...

    yes, also gcc is for compile c/c++ code and irun is for compile hdl/systemc/system verilog and elaboration and simulation!
  7. L

    General question about digital design

    HDL is hardware discription language , which RTL is register transmitted level
  8. L

    delay measurement with modelsim

    If you don't use SDF back annotate, you won't have any delay between input and output!
  9. L

    Error in simulating a gate-level netlist in Modelsim

    you should have the vhd file for gate level simulation , not using write_lib command to generate the code!
  10. L

    UVM assert(req.randomize(clkgen) with {clock.period ==period ;}); doesn't work in VCS

    Can you list all your clkgen sv code?
  11. L

    finding registers in RTL or gate level design with associated clock

    you can use spyglass tool to do this thing!
  12. L

    needed simulator supporting systemverilog for free

    If you use ncsim or vcs,you need license! Modelsim can support ovm/uvm, you can have a try!
  13. L

    VCS simulation error concerning memory (32-bit)

    Re: VCS simulation error you have a lot of dumping code?
  14. L

    Architectural issues in ASIC processor design

    you need to do RTL design or architecture design?
  15. L

    any one using jaspergold formal verification tool for property checking

    you use this tool to do formal check?
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