Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi, guys
i'm a icer.
7years digital ic design experiences.
7years professional digital ic verification experiences.
familarize:
verilog, systemverilog, vmm ,uvm ,xml ,perl ,c ,c++ ,design pattern ,csh ,vcs ,modelsim,and so on
specially, i familarize the source code of vmm and uvm and will...
i have finished a design in verilog;nmlr is the global reset signal and is low active; i have a development board of stratix(ep1s10f780c6). ac9 is stratix's
resetsignal input pin;i assign nmlr to ac9;but i find it can't be reseted; how can i do?
i shoud insert some special logic between the...
always@(posedge s3 or posedge addpc);
begin
if(addpc) pc<=pctemp+1'b1;
else begin pc<=13'b0000000000111;pctemp<=pctemp+1'b1;end
end
warning:pctemp isn't the always control envent!
///////////////////////////////////////////////////////////////////////////////////////////////ffunction...
input signals a,b,c.d,is unrelative;output signal enosc is a register variable;
if a or b 's posedge come ,we set enosc one;if c's negedge come we set enosc
zero.else we keep enosc unchange;
who can give me the code of verilog?
here is my initial code,but it can't meet my requirement...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
