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i think ur library may be corrupted........the contact information is supposed to be present in the UMC_180 library.......are u gettin' problem only for contacts??........or for some other instances also......??.........
for checkin' DRC wat i use is ASSURA_DRC umc180 with rule set file DRC...
Its very easy............design an ordinary D flip flop using transmission gates and inverters.........at the output 'q' terminal place one NAND2 gate with one input as the 'q' terminal of the flip flop and the other as 'Presetbar' this ll implement active low asynchronous preset input based D...
The question s not quite clear...........it looks like a simple digital logic............AND gate or something with one input '1' and other as input push button........Plz explain the question once again......
HI.........one of my friend is doin project on interconnects......His design has 3 modules......When he s using only
the 1st 2 modules, the output at every point is comin' quite perfectly....... Now when he simply inserts the 3rd
module into the design, which is driven by the 2nd module, the...
if i am the cell designer and i am plannin to design the standard latches.......then wat all things to take care??........ and in between the latches doesnt ve setup and hold times.....they ve recovery and removal times i guess...........
Wat happens if the master is triggered by a clock and slave by the same clock after passing thro an inverter??..........master is off as soon as the clock goes low........is hold violation possible there??.........because slave is getting triggered later compared to master.........
I think setup thing is related to master and hold is related to slave latch......
because before the clock edge the master latches data into it.......and data has to be stable "setup" time before clock edge. setup time in other words is the time required to charge/discharge the input capacitance...
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