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What is the concept of overclock with clock gap?
I have an example which could explain my problem more precisely:
the input signal width to my block is 16bits @sys16_clk; the 16 bits vectors will be concatenated to a 66 bits vector @ sys16_clk. It's impossible to do that because the...
Currently I have three LUT ROM module written by verilog. The thing is under different condition, the behavior module I am writing will work on the data from only one certain LUT of the three. How could I deal with the code structure? I know I may need to initialize all of the three modules in...
But the problem is I don't know how to find the total negtive slack in my chip. The only thing I could get is the worst negtive slack and how many total paths as shown below:
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all |...
Thank you huckle. But what if my negtive slack is possitive? Say using 5ns clock and worst negative slack is 0.5ns. Does it mean I only need 5-0.5 ns to finish my calculation?
Lien
Hi guys,
I am a newbie in SoC Encounter but I need to figure out how many clock cycles for my chip to finish one calculation. So do u know if I could get this clock cycles from SoC Encounter by using any command or method?
Thank you.
Best,
Lien
Thank you bigdogguru and srizbf. I have figured out that there is trully a mistake when I configure the PATH variable(it should be pointed to the \bin of Modelsim directory). Now AutoESL can recognize Modelsim and gcc. I am running some simple example to see the simulation results. And also I...
Hi everyone,
I want to install gcc compiler in Modelsim se 6.5c because I need to use AutoESL to communicate with Modelsim. After copied all the thing from gcc-4.2.1-mingw32.zip to Modelsim installation foler, I could simulate systemC in Modelsim but AutoESL still complains:
[SIM-57] Did not...
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