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Recent content by libo

  1. L

    How to verify a 32 bit counter?

    32 bit counter i think the simpliest way is connect it in the real system, and check if it can work.
  2. L

    question about IC designflow

    i think designing from gate level to transistor leve is a real hard job if no cad tools. The solution is reuse the std cell.
  3. L

    Opinions on VCS 7.0 software

    V C S 7.0 VCS is a very fast simulation tool in RTL
  4. L

    how can i build a platform to practising verilog or vhdl

    Hi,all I am a student learning microelectronics. Recently i have learned verilog and vhdl,but l am unfirmliar with the develop tools. l want a platform that can simulation , sythesis from RTL code to gate level netlist and verification. l think practisice is important. but how can i build this...
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