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Hello,
I am trying to perform trial by using the DCT (DC topographical) vs the norma DC flow.
I have problem with DCT timing clean but PT has timing violation. I guess it is something related to the RC calculation where the DCT has the DEF information but PT is purely dependent on the...
Hi,
I am using the synosys PTPX 2010 to generate the power waveform (fsbd) file but it is in latest 4.2 version.
But my viewer tool Cosmoscope (2007 version) can only support up to version4.1. Anyway I can downconvert the fsdb from version 4.2 to 4.1 or wise versa?
Thanks
Hi I am Xilinx player for a long time, now gonna fpga prototyping on altera board. Want to know what's the tool name in QuartusII which equivalent to Chipscope in Xilinx. Thanks.
Hi Thanks for reply, I am asking, how to achieve it.
Like the function
assign z[0] = b[0]&a[0]^b[1]&a[7]^b[2]&a[6]^b[3]&a[5]^b[4]&a[4]^b[5]&a[3]^b[5]&a[7]^b[6]&a[2]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[5]^b[7]&a[6]^b[7]&a[7];
Why is this function?? How to get into this function?
Hi guys,
I am implementing ReedSolomon Code(256,191) with 8bits per symbol
I found some of the online code for Galois Field Multiplier 256 as followed. Who can tell me how to come out with this kind of XOR ?
module gf256mult(a, b, z);
input [7:0] a;
input [7:0] b;
output [7:0] z;
assign z[0]...
galois multiplier
Hi guys,
I am implementing ReedSolomon Code(256,191) with 8bits per symbol
I found some of the online code for Galois Field Multiplier 256 as followed. Who can tell me how to come out with this kind of XOR ?
module gf256mult(a, b, z);
input [7:0] a;
input [7:0] b...
fault coverage netlist
Hi all,
I am just wondering, do we need to run the code coverage at the gate-level netlist?
Can the code coverage from cadence support code coverage at the gate-level netlist? Thanks
conv_std_logic_vector verilog
Hi Guys,
I need to convert this VHDL code into the Verilog. I tried it with the online free converter software, the end result still have errors, can please advice over here?
VHDL CODE as followed
library IEEE;
use IEEE.std_logic_1164.all;
use...
Hi,
I know how to perform single test case ncverilog code coverage, but now I am required to perform test coverage for 100 available test cases files. Anyone know how to do it?
For the DDR2 and DDR3, there are
1. ODT (On die termination)
2. TDQS (Termination Data Q strobe)
Actually, what's the reason of these Termination is needed? Use on what time ? Also the ODT pin is for what purpose?
In DDR3, there's this BC# option where we only read out the highbytes of DQ...
Hi guys,
A ) In normal syn FIFO design, the data out is not registered.
assign data_out = MEM[RD_PTR];
B) If we would like to register the data_out as
always @(posedge clk)
data_out <= MEM[RD_PTR];
Compared the method, the B (registered data_out) will read out the data_out 1 clk...
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